1. Field of the Invention
The present invention relates in general to a process of designing, simulating, fabricating, testing and interconnecting integrated circuits (ICs), and in particular to a method for fully integrating the interconnect systems that are to connect ICs to external circuits into all stages of that process.
2. Description of Related Art
Integrated Circuit Process Flow
FIG. 1 illustrates a typical prior art process of designing, fabricating, testing, and connecting an integrated circuit (IC). A design engineer initially develops a design specification (step 400) abstractly describing the functionality and overall architecture of the IC and then develops a high-level hardware description language (HDL) model of the IC describing how data flows between clocked registers and how the design processes that data (step 402). The design engineer also programs a circuit simulator (step 404) to simulate circuit behavior based on the HDL circuit model and may iteratively adjust and simulate the HDL model until verifying that the circuit logic is correct. Since the HDL model is a relatively high level behavioral model of the circuit, simulation can verify circuit logic at step 404 but cannot verify circuit timing because it does not take into account various constraints of the particular semiconductor technology that will implement the IC.
Thereafter, the design engineer usually employs computer-aided logic synthesis tools (step 406) to convert the high-level HDL circuit model into a lower-level, technology-specific, behavioral model of the circuit such as a netlist. A netlist model typically describes the behavior of circuit components based on models provided by a cell library 410. Each cell of cell library 410 includes both netlist-level behavioral models and structural models (mask layouts) for each circuit component that may be incorporated into an IC. Cell library 410 may include cells describing low level circuit components such as individual resistors and transistors as well as higher level standard circuit components such as logic gates, memories and central processing units.
During the iterative, synthesis process the design engineer uses a simulator and other tools to verify circuit operation based on the netlist model (step 412) and may iteratively adjust the HDL model to produce a netlist model that satisfies various constraints on circuit operation defined in the specification and incorporated into the HDL model. Since the netlist model is more closely related to the eventual physical realization of the IC than the HDL model, simulation and special timing verification tools can verify both circuit logic and timing constraints. However, timing constraints verification at this stage of the design may not be entirely accurate since the netlist model does not specify the actual physical positions on an IC chip of the cells that will form the circuit or the actual lengths and impedance characteristics of signal paths between those cells.
Having verified the logic and timing of the netlist circuit model, the design engineer employs additional computer-aided design tools to establish a floorplan (step 414) fixing locations of the IC's input/output (I/O) terminals and fixing the positions of various large, high level circuit modules included in cell library 410 that are to be placed in particular areas of the IC substrate. Placement and routing tools establish the detailed layout of the various layers of IC, determining where each cell of the IC is to be placed and how the conductors interconnecting those cells are to be routed (step 418). In addition to a behavioral model of a circuit component, each component cell of cell library 410 also includes a structural model (mask layout) of the circuit component that can be incorporated into the IC layout. The CAD tools performing the floorplanning, placement and routing functions iteratively vary the IC design, subjecting each variation to simulation and verification (step 422) to determine how well it satisfies the various timing and logic constraints imposed by the specification. Timing verification at this point is more accurate than the timing verification carried out on netlist at step 412 because it takes into account the actual physical layout of the cells and their interconnections.
The output of the placement and placement and routing process 418 is a structural model of the IC in the form of a set of masks telling an IC manufacturer how to fabricate the various layers of the IC. When an IC fabricated on a semiconductor wafer includes a “repairable” embedded memory, a memory test is usually performed (step 428) while the IC is still in the form of a die on the wafer. “Repairable” memories typically have one or more “spare” rows or columns of memory cells that can replace a row or column containing one or more defective cells. The results of the memory test are subjected to “redundancy analysis” (step 430) to determine how to best allocate spare rows and/or columns to replace the rows and/or columns containing defective cells. The memory is then repaired (step 432) using lasers or other means to appropriately alter signal path routing within the IC so that spare rows and/or columns of cells are substituted for rows and columns having defective cells.
After repairing the memory (step 432), or immediately after fabrication (step 424) when the IC has no repairable memory, the wafer is “diced” to separate the individual die (step 434) and packaged (step 436). The packaged IC may the be subjected to a “burn-in” process (step 438) wherein it is heated in an oven to place it under the kind of heat stress they it may encounter in its working environment. Thereafter the packaged IC is subjected to logic and parametric testing (step 440). The packaged IC is later mounted on a circuit board in its intended operating environment (step 442). The IC testing step 440 can be carried out before the dicing step 434 while the IC is still in the form of a die on the wafer.
Interconnect Systems
As a part of the IC design process, IC designers must concern themselves with the structures that connect nodes of an IC to external circuits. In a typical packaged IC, each circuit node that is to communicate with external circuits is linked to a bond pad on the surface of the IC chip. A bond wire connects the bond pad to a conductive leg extending from the package surrounding the IC chip. When the IC is mounted on a printed circuit board (PCB) the package leg is usually soldered to a PCB trace on the surface of the PCB. When bond pads of one or more other ICs mounted on the PCB are linked to the PCB trace, the bond pads, bond wires, package legs, and the PCB trace form an interconnect system for conveying signals between nodes of two or more ICs. Other interconnect systems are also used, For example, in “solder ball” IC packages the bond wires link the IC pads to balls of solder on the underside of the package that bond to PCB traces when the IC is installed on a PCB.
Spring contact interconnects are becoming popular replacements for bond wire and solder ball interconnect technologies in many applications because they eliminate the need for IC packaging and because they provide a number of other advantages. FIGS. 2 and 3 are partial sectional elevation views of an IC 10 and an IC 20 employing small wire-spring contacts 16. The circuits implemented by IC 10 are implemented on a silicon wafer substrate 12. A separate bond pad 14 is formed at the surface of substrate 12 for each of the IC's I/O signals. In the IC 10 of FIG. 2, a conductive wire-spring contact 16 is attached to each bond pad 14. Each wire-spring contact 16 is suitably formed, for example, by a gold wire welded to the bond pad 14 and coated with a resilient alloy. The unpackaged IC 10 can be installed directly on a printed circuit board (PCB) 17 with the tip 18 of each wire-spring contact 16 contacting a trace 19 on the surface of PCB 17.
In IC 20, as illustrated in FIG. 3, the wire-spring contact 16 can be mounted remote from a bond pad 14 on substrate 12 when linked to the bond pad 14 via a conductive trace 22 formed on a “redistribution layer” on the surface of an IC 20. Trace 22 is attached to bond pad 14 through a conductive adhesion layer 28 and isolated from portions of IC 12 other than bond pad 14 by insulating polyimide layers 24 and 26.
FIG. 4 is a simplified, partial sectional elevation view of an IC 30 employing another kind of spring contact, a “litho-spring” contact 32. An insulating passivation layer (e.g., polyimide) 35 disposed on the surface of substrate 34 includes an opening 36 immediately above a contact pad 37. A conductive layer 39 (e.g., titanium-tungsten) is deposited on the surface of passivation layer 35 with the sidewalls of opening above contact pad 37 making electrical contact with contact pad 37. A layer 38 of masking material (e.g., photoresist) is then deposited onto layer 35 and patterned by photolithographic techniques to include an opening above contact pad 37 extending through masking layer 38 to conductive layer 39. Layer 38 also includes a bump 40 forming a base for the wire-spring contact's tip 42. A conductive seed layer 41 (e.g., gold) is then deposited over masking layer 38 and lithographically etched to form the basic shape of contact 32. A resilient, conductive contact layer 43 (e.g., nickel) is then plated onto seed layer 41. The photoresist masking layer 38 is then removed with a solvent (e.g., acetone), and other remaining layers (e.g. part of layer 39) are removed using suitable techniques. In the completed wire-spring contact 32, tip 42 has freedom to flex vertically when pressed against a trace 45 on a circuit board 46.
Attenuation and Distortion in Interconnect Systems
In high frequency applications an interconnect system can severely attenuate and distort signals passing between the IC and external circuits. The conventional approach to reducing the amount of signal distortion and attenuation caused by the interconnect system has been to minimize the series inductance and shunt capacitance of the interconnect system. Much of the inductance in packaged IC interconnect system comes from bond wires and package legs or spring contacts. Designers try to minimize that inductance by keeping the bond wires and package legs or spring contacts as short as possible. Interconnect system capacitance arises mainly from the capacitances of bond pads and printed circuit board (PCB) traces, and the capacitances of terminating devices within the IC such as drivers, receivers and electrostatic discharge protection (ESD device) devices. Designers try to minimize the interconnect system capacitance when designing such components. However, while minimizing interconnect system inductance and capacitances can help improve bandwidth, flatten frequency response and reduce signal distortion, it is not possible to completely eliminate interconnect system inductance and capacitance. Thus some level of signal distortion and attenuation in an interconnect system is inevitable, and can become problematic particularly at high signal frequencies.
Interconnect System Design
While IC designers must sometimes be concerned with the frequency response of an entire interconnect system linking a node of an IC to a node of an external circuit, the design tools they work with treat the internal and external components of an interconnect system in a somewhat fragmented manner. Conventional IC cell libraries typically include separate physical and behavioral models of various portions of an IC interconnect system that are internal to the IC such as drivers, receivers, ESD devices, bond pads and the like. However, such cell libraries do not include models of the portions of the interconnect system external to an IC such as bond wires and package legs, litho-spring or wire-spring contacts, microstrip traces, circuit board vias and the like because they are not part of the IC.
However, since the external portions of an interconnect system influence the behavior of an IC at its I/O terminals, a design engineer may provide a behavioral model of the external portions of the interconnect system that can be incorporated into the HDL and netlist circuit models for use by simulation and verification tools. Such models usually depict the external portions of an interconnect system as a transmission line of a standard characteristic impedance (typically 50 Ohms) that is terminated with a specified load. The simulation and verification tools employed at steps 412 and 422 of the IC process flow of FIG. 1 can make reasonably accurate predictions of circuit behavior at the bond pads when designers endeavor to make the external portions of the interconnect systems and external loads conform to the models.
IC designers typically specify uniform interconnect systems for all IC terminals partly because IC manufacturing processes readily lend themselves to interconnect uniformity and partly because it is difficult and time-consuming to custom design an interconnect system for each IC terminal. However, while interconnect systems for all terminals of an IC are usually standardized, the frequency response and current-carrying capability of the standard interconnect system may not be ideally suited for all of the IC's I/O, power or ground signals since not all such signals are similar in nature.
For example, suppose an IC has both low frequency analog I/O signals and high frequency digital I/O signals. While a designer also might want the interconnect system conveying the analog signals to provide very low distortion at low signal frequencies and to block high frequency noise, the designer might want the interconnect systems conveying the high frequency digital output signals to have a high bandwidth. Thus, if we use the same interconnect system for each kind of signal, the interconnect system can be a limiting factor in IC design. For example when a standard interconnect system cannot handle a high frequency digital I/O signal, an IC may be designed to use two or more lower frequency I/O signals in its place. Or when an IC's standard pin size is not sufficient to handle all of the IC's power and ground currents, several pins may be needed to supply power and ground to an IC. When we employ such measures to avoid customizing interconnect systems for individual IC terminals we can increase both the size and cost of an IC.
IC Tester Interconnects
As I/O signal frequencies increase, the design of structures we use to link a wafer-level IC tester to test points on an IC wafer becomes increasingly problematic. When wafer-level IC tester interconnect systems do not have the same frequency response characteristics as interconnect systems employed in an IC's intended operating environment, then many ICs that would operate properly in their intended operating environment can fail tests and be rejected or de-rated.
One difficulty in conforming test and operating environment interconnects arises because IC I/O signals typically must travel longer distances in a test environment than in its intended operating environment. FIG. 5 is a simplified side elevation view of a typical wafer-level IC tester 90 that can carry out a memory test at step 428 of FIG. 1 or a logic or parametric test on an IC while still in wafer from. Tester 90 includes a test head 92 containing printed circuit boards implementing the circuits that test a wafer 94. The test circuits are usually organized into a set of similar “channels”, with each channel including all the circuitry needed to generate a test signal input to one test point on the wafer and to monitor any wafer output signal produced at that test point. Each channel usually has a single bi-directional input/output (I/O) port through which it communicates with an IC bond pad on the surface of wafer 94.
A “prober” 98 holding wafer 94 includes a probe card 100 having a set of probes 102 for accessing bond pads on the surface of one or more ICs on wafer 94. An interconnect structure 104 residing between the test head 92 and wafer 98 provides signal paths between the tester's I/O ports and probe card 100. Thus a test signal produced by test head 92 travels to an I/O terminal of wafer 94 through a signal path extending through interconnect structure 104, probe card 100 and probes 102. An IC output signal would travel over a similar path in an opposite direction.
Such a signal path can differ substantially both in length and nature from the signal path (e.g., bond wires, pins and PCB traces) though which that IC I/O terminal will eventually communicate when it is in its intended operating environment. The frequency response characteristics of the test signal path may therefore also differ substantially from the behavioral models the design engineer supplied to simulation and verification tools during the IC design process. Such discrepancies between an interconnect system's behavioral model employed during the IC design phase and its actual test and operating environment implementation can cause ICs that would function properly in their intended operating environments to fail tests and be discarded or de-rated.
IC manufacturers like to test an IC while still in wafer form because it allows them to avoid the cost of packaging defective ICs. However high frequency ICs are often tested after they are packaged (as illustrated in, FIG. 1) because the wafer-level test environment fails to account for the influence of the bond wires and package legs on IC performance.
What is needed is a method for designing, simulating, fabricating, testing and interconnecting ICs wherein a designer can easily adapt the interconnect system for each of an IC's terminals to satisfy the requirements of the particular signal it is to convey, and wherein the signal paths in the IC's wafer-level testing environment and in its intended operating environment can substantially match their behavioral models employed during the IC design process.